MTI  TN1014:     Stitch Vias

 

Stitch vias (and via fences) are often used to tie ground planes and ground metal pours to planes.  The common rule of thumb is to locate stitch vias no further apart than  and preferably as often as. 

 

There are numerous reasons to use ground via stitching on a multilayer PCB.   Some of the reasons are:

w     Prevention of coupling into nearby traces and metal pour.

w     Prevention of waveguide signal propagation, shielding/isolation of circuit blocks, and the reduction of slot radiation from the edges of a PCB.

w     Completion of a robust power distribution design.  Reduction of series inductance to active and passive parts.  For more detailed info on PDN (power distribution networks) in PCB, see [2].

w     Signal integrity, in particular for signals that transition planes.

w     Thermal reasons (not covered in this tech note).

 

Rules of thumb are useful, but nothing beats analysis and a valid simulation for support.  Two analytical approaches are illustrated and explained.  This technical note continues with an examination of stitch via usage, and a rationale for selecting the distance/density of stitch vias. 

 

 

First, a key consideration; .  This is the guided wavelength.  We know that the free space wavelength of a sine wave is simply:

 

        or        

 

but in a dielectric, the wavelength is shorter, and must be multiplied by ; the inverse of the square root of the dielectric constant.  The dielectric constant number to use is obvious if we are interested in coax, or striplines, since the signal conductor is buried in the dielectric.  For microstrip, a portion of the electric field is in air, and the effective dielectric constant must be used [3], [4], [5].   For microstrip on FR4 type material (), results in an .  In this case, the guided wavelength will be ~0.58 times the free space wavelength.   The equations in [3] are one way to approximate the effective dielectric constant, however, the best way to obtain the actual effective dielectric constant for your particular application is by using electromagnetic field solver analysis.

 

I have had no trouble in finding guidance in reference books regarding stitch vias when it came to inner planes and waveguide modes.  However, no luck in looking for a rationale for stitch vias to tie down a metal ground pour near microstrip on the outer layers of a PCB.  The approach I favor is based on coupled microstrip.

 


 

Let’s take a look at a simple example:

Line Callout 3: Top layer ground pour 10 mils away from the microstrip, about   long at 2GHz
Line Callout 3: A single ground via ties the top layer metal pour to the ground plane
 

 

 


Line Callout 3: 1” long microstrip, 10 mils wide, FR4 dielectric of 4.0, dielectric height = 4.5mils.

 

 

 

As we know from coupled microstrip theory [6], the best coupling (our worst problems) will occur when the coupled length is ,  ,

We use an EM field solver to plot the reflections (S11) caused by the nearby ground pour:

 

Line Callout 3:   Line Callout 3:   Line Callout 3:

 

A significant reflection is seen at ,  and the reflections are huge at   and .  Obviously not a problem if your signal is a 433MHz sine wave, but large reflections would certainly corrupt the edges of a 1.25GHz (2.5 Gbit) rectangular signal.


Adding a few stitch vias:

 

2 vias:                                                                                      3 vias:

 

Again, we analyze and plot the reflections on our microstrip:

Line Callout 3: 3 via
 


Line Callout 3: 1 viaLine Callout 3: 2 via

 

In short, vias placed every  has the effect of reducing the coupling at , and eliminating problems up to .  This would be OK for sine waves at , but perhaps not quite sufficient for digital signals where we want to preserve signal integrity.    Recall  that to preserve a digital signal’s edges, we typically consider up to at least the  5th harmonic of the digital signal’s fundamental frequency.    Thus the guideline to locate stitch vias no further apart than  and preferably as often as looks pretty good.

 

 

 

 

 

 

 

 


We are also interested in using stitch vias to help us out with a PCB’s internal power/ground planes. 

 

 

We can consider the parallel planes in a PCB as a rectangular resonant cavity with physical size of a x b x d, see [1]:

 

 

Pozar notes that for b<a<d, the dominant resonant mode will be the TE101 mode.   Since we do not normally fabricate our PC boards with magnetic materials, μr = 1. 

 

Side note:  With regards to waveguide signal propagation between two parallel conductive planes, there is some interesting current work in making constructive use of this effect.  At this time, the key phrase is “Substrate Integrated Waveguide (SIW)”.

 

The equation (all dimensions in meters) simplifies to:

 

 

 

For example:   FR4 like material (εr ~ 4)

 

 

Where m,l = 1, 2 3… , and a,d are the width and length of the PCB in meters.   In many cases we can pretty much ignore the thickness (plane separation distance) in the equations above.

 


The following example considers a 6 inch by 10 inch FR4 board with a power plane and ground plane.   Using the equation above, we find that the first four resonances are at 573.52MHz, 768.19MHz, and 1026.88MHz, and 1147.03MHz, followed by many more resonances above 1200MHz.

 

After placing a stripline port on either side of the plane pair (see the following page).  Shorting each of the striplines to the ground plane,  we can evaluate the coupling between the short lines on either end of the board:

 

 

Note:   The magnitude of each resonance is heavily influenced by our coupling into the waveguide.  As expected, our very short shorted striplines do not couple well at low frequencies. We can also take a look at the current density in one of the power planes as seen in the following page.

 


At 573MHz:

Line Callout 3: Short stripline ports shorted at the end to the ground plane.
Overall size:  6x10”

At 1147MHz:


We can perform a simple experiment by placing a single sparse via fence across the width of the board.  The vias are spaced about 0.5 inch apart:

Simulating the structure shows that the coupling is reduced by about 40dB:

Line Callout 3: Waveguide coupling – no via fence
 


Line Callout 3: Waveguide coupling – with via fence

 

 

 


We can do much better at lower frequencies with a stitch via field.  The field has stitch vias on roughly 1 inch centers between the two planes:

Line Callout 3: Waveguide coupling – no via field
 


Line Callout 3: Waveguide coupling – with via field

 

 

 

The density of stitch vias, and their location depends entirely on what is critical in your application (for example: shielding, isolation, signal or PDN quality,.   As usual, an analysis of the system requirements as well as possible coupling is highly recommended.  Given available resources, it is to our advantage to support the analysis with field solver simulations, then follow up with measurements on a test board or with appropriate tests on the first fabricated boards (sneaking in engineering measurement capability is a time-honored tradition).

 

 


References:

 

[1] David M. Pozar.  Microwave Engineering, 2nd Edition.  Hoboken, NJ: John Wiley & Sons, 1998.

[2]  Istvan Novak and Jason Miller, Frequency Domain Characterization of Power Distribution Networks.  Norwood, MA:  Artech House, 2007.

[3] E. Hammerstad and O. Jensen, “Accurate Models for Microstrip Computer-Aided Design,” Microwave Symposium Digest, 1980 MTT-S International, pp407-409

[4] Manfred Kirschning and Rolf Jansen, “Accurate Wide-Range Design Equations for the Frequency Dependent Characteristic of Parallel Coupled Microstrip Lines,”  IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-32, No 1, pp83-90, Jan. 1984.

[5] Hong and Lancaster.  Microstrip Filters for RF/Microwave Applications.  New York, NY: John Wiley & Sons, 2001.

[6] Mongia, Bahl and Bhartia.  RF and Microwave Coupled-Line Circuits..  Norwood, MA: Artech House, 1999.